Javier Mora de Sambricio

photo of Javier Mora de Sambricio

Position

Ph.D. student

Contact

javier.morad@upm.es

Academic Degrees

Nov 2011. B.Sc. and M.Sc. on Industrial Engineering. Universidad Politécnica de Madrid (UPM).

Sep 2013. M.Sc. on Industrial Electronics. Universidad Politécnica de Madrid (UPM).

research lines

Digital circuit design, FPGA design, dynamic partial reconfiguration, evolvable hardware

short cv

Javier Mora received the BSc degree in Industrial Engineering from the Universidad Politécnica de Madrid (UPM), Spain, in 2011, and the MSc in Industrial Electronics in 2013 from the same University.  He is currently working toward the PhD degree in Industrial Electronics at UPM.  He has been a grant-holding researcher at the Centre of Industrial Electronics (CEI), UPM, and has later held an FPI grant from the Spanish Ministry of Economy and Competitiveness.  His current research area is in the field of evolvable hardware and dynamic partial reconfiguration of FPGAs.
Publications:
  • J. Mora and E. de la Torre (2018). Accelerating the evolution of a systolic array-based evolvable hardware system. Microprocessors and Microsystems, 56:144–156 https://doi.org/10.1016/j.micpro.2017.12.001.
  • J. Mora, A. Otero, E. de la Torre and T. Riesgo, “Fast and compact evolvable systolic arrays on dynamically reconfigurable FPGAs,” 2015 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), Bremen, 2015, pp. 1-7. https://doi.org/10.1109/ReCoSoC.2015.7238087
  • Á. Gallego, J. Mora, A. Otero, E. de la Torre and T. Riesgo, “A scalable evolvable hardware processing array,” 2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig), Cancun, 2013, pp. 1-7. https://doi.org/10.1109/ReConFig.2013.6732266
  • J. Mora, Á. Gallego, A. Otero, E. de la Torre and T. Riesgo, “Noise-agnostic adaptive image filtering without training references on an evolvable hardware platform,” 2013 Conference on Design and Architectures for Signal and Image Processing (DASIP), Cagliari, 2013, pp. 182-189.http://ieeexplore.ieee.org/document/6661538/
  • J. Mora, Á. Gallego, A. Otero, B. López, E. de la Torre and T. Riesgo, “A noise-agnostic self-adaptive image processing application based on evolvable hardware,” 2013 Conference on Design and Architectures for Signal and Image Processing (DASIP), Cagliari, 2013, pp. 351-352 (demo).http://ieeexplore.ieee.org/document/6661571/
  • Filip Veljković, Javier Mora, Teresa Riesgo, Luis Berrojo Valero, Raúl Regada Sánchez, Ángel Álvaro Sánchez and Eduardo de la Torre, “Prospection of Reconfiguration Capabilities using Space Qualified SRAM-based FPGAs for a Satellite Communications Application”, 31st AIAA International Communications Satellite Systems Conference (ICSSC), Florence, 2013. https://doi.org/10.2514/6.2013-5683
  • Á. Gallego, J. Mora, A. Otero, R. Salvador, E. de la Torre and T. Riesgo, “A Novel FPGA-based Evolvable Hardware System Based on Multiple Processing Arrays,” 2013 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW), Cambridge, MA, 2013, pp. 182-191.https://doi.org/10.1109/IPDPSW.2013.56
  • Á. Gallego, J. Mora, A. Otero, B. López, E. de la Torre and T. Riesgo, “A self-adaptive image processing application based on evolvable and scalable hardware,” 2013 23rd International Conference on Field programmable Logic and Applications (FPL), Porto, 2013, pp. 1-1 (demo). https://doi.org/10.1109/FPL.2013.6645631
  • R. Salvador, A. Otero, J. Mora, E. de la Torre, T. Riesgo and L. Sekanina, “Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing,” in IEEE Transactions on Computers, vol. 62, no. 8, pp. 1481-1493, Aug. 2013. https://doi.org/10.1109/TC.2013.78
  • R. Salvador, A. Otero, J. Mora, E. de la Torre, T. Riesgo and L. Sekanina, “Implementation techniques for evolvable HW systems: virtual VS. dynamic reconfiguration,” 22nd International Conference on Field Programmable Logic and Applications (FPL), Oslo, 2012, pp. 547-550. https://doi.org/10.1109/FPL.2012.6339376
  • R. Salvador, A. Otero, J. Mora, E. de la Torre, L. Sekanina and T. Riesgo, “Fault Tolerance Analysis and Self-Healing Strategy of Autonomous, Evolvable Hardware Systems,” 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), Cancun, 2011, pp. 164-169. https://doi.org/10.1109/ReConFig.2011.37
  • A. Otero, R. Salvador, J. Mora, E. de la Torre, T. Riesgo and L. Sekanina, “A fast Reconfigurable 2D HW core architecture on FPGAs for evolvable Self-Adaptive Systems,” 2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), San Diego, CA, 2011, pp. 336-343. https://doi.org/10.1109/AHS.2011.5963956
  • R. Salvador, A. Otero, J. Mora, E. de la Torre, T. Riesgo and L. Sekanina, “Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support,” 2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), San Diego, CA, 2011, pp. 184-191.https://doi.org/10.1109/AHS.2011.5963934