Otero, A. ;Krasteva, Y.; De la Torre, E.; Riesgo, T.; ,”Generic Systolic Array for Run-Time Scalable Cores”, In the Proceedings of the 6th International Symposium on Applied Reconfigurable Computing (ARC 2010), Bangkok, Thailand, March 2010 (Published like Lecture Notes on Computer Science LNCS 5992) PDF
Otero, A.; de la Torre, E.; Riesgo, T.; Krasteva, Y.E.; , “Run-Time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs,” In the Proceedings of the International Conference on Field Programmable Logic and Applications (FPL 2010), 2010, vol., no., pp.70-76, Aug. 31 2010-Sept. 2 2010 PDF
Otero, A.; Morales-Cas, A.; Portilla, J.; de la Torre, E.; Riesgo, T.; , “A Modular Peripheral to Support Self-Reconfiguration in SoCs,” 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2010), 2010, vol., no., pp.88-95, 1-3 Sept. 2010 PDF
[4] Otero, A.; Pujó, R.; Portilla, J.; de la Torre, E.; Riesgo, T.; , “Feasibility of HW genetic algorithms for profile selection in reconfigurable autonomous embedded systems”, ”, In the Proceedings of the XXV Conference on Design of Circuits and Integrated Systems, 17-19 November 2010, Lanzarote, Spain (DCIS 2010)
Cervero, T.; Otero, A.;, López, S.; De La Torre, E.; Callicó, G.;,Sarmiento, R.; Riesgo, T. ; ”A Novel Scalable Deblocking Filter Architecture for H.264/AVC and SVC video codecs”, In the Proceedings of the 2011 IEEE International Conference on Multimedia and Expo. (ICME 2011) PDF
Cervero, T., Otero A., De la Torre, E., López, S., Callicó G., Riesgo, T. and Sarmiento R; “Scalable 2D architecture for H.264 SVC deblocking filter with reconfiguration capabilities for on-demand adaptation ” Proceedings of the SPIE 2011, vol. 8067, April 2011.
Otero, A.; LLinás, M.; Portilla, J.; de la Torre, E.; Riesgo, T.; “Cost and energy efficient reconfigurable embedded platform using Spartan-6” Proceedings of the SPIE 2011, vol. 8067, April 2011.
Salvador, Ruben; Otero, A.; Mora, J.; de la Torre, E.; Riesgo, Teresa; Sekanina, Lukas; ,” Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support”, In the Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2011), 6-9 Junio 2011. PDF
Otero, A.; Salvador, Ruben; Mora, J.; de la Torre, E.; Riesgo, Teresa; Sekanina, Lukas; , “A Fast Reconfigurable 2D HW Core Architecture on FPGAs for Evolvable Self-Adaptive Systems” , In the Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2011), 6-9 Junio 2011 PDF
Cervero, T., Otero A., De la Torre, E., López, S., Callicó G., Riesgo, T. and Sarmiento R; “Framework adaptable y reconfigurable dinámicamente para procesamiento de vídeo: aplicación a la etapa de filtrado adaptativo en sistemas de compresión de vídeo H.264/AVC y SVC”, In the Proceedings of Jornadas de Computación Reconfigurable y Arquitecturas (JCRA 2011)
Otero, A.; Torre, E. De La; Riesgo, T.; Cervero, T.; Lopez, S.; Callico, G.; Sarmiento, R.; , “Run-Time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs,” In the Proceedings of the International Conference on Field Programmable Logic and Applications (FPL 2011), 2011, vol., no., pp.369-375, 5-7 Sept. 2011 doi: 10.1109/FPL.2011.72 PDF
Salvador, Ruben; Otero, A.; Mora, J.; de la Torre, E.; Riesgo, Teresa; Sekanina, Lukas; ,” Fault Tolerance Analysis and Self-Healing Strategy of Autonomous, Evolvable Hardware Systems”, Proceedings of the 2011 International Conference on ReConFigurable Computing and FPGA (RECONFIG2011) PDF
Otero, A.; Salvador, Ruben; Mora, J.; de la Torre, E.; Riesgo, Teresa; Sekanina, Lukas; , “2D Reconfigurable Systolic Core Architecture for Evolvable Systems” ”, Proceedings of the XXVI Conference on Design of Circuits and Integrated Systems (DCIS2011)
Pilato, C; Cazzaniga, A; Durelli, G; Otero, A; Sciuto, D; Santambrogio, M; “On The Automatic Integration of Hardware Accelerators into FPGA-based Embedded Systems”. To appear in the In the Proceedings of the International Conference on Field Programmable Logic and Applications (FPL2012)
Salvador, R; Otero, A.; Mora, J.; de la Torre, E.; Riesgo, Teresa; Sekanina, Lukas; ,”Implementation techniques for evolvable HW systems: virtual vs. dynamic reconfiguration” ”. To appear in the In the Proceedings of the International Conference on Field Programmable Logic and Applications (FPL2012)
Otero, A.; de la Torre, E.; Riesgo, Teresa; “Dreams: A Tool for the design of Dynamically Reconfigurable Embedded and Modular Systems“. To appear in the Proceedings of the 2012 International Conference on ReConFigurable Computing and FPGA (RECONFIG2012)
Wei, He; Otero, A.; de la Torre, E.; Riesgo, Teresa; “Automatic Generation of Identical Routing Pairs for FPGA Implemented DPL Logic“. To appear in the Proceedings of the 2012 International Conference on ReConFigurable Computing and FPGA (RECONFIG2012)
Regarding International Journals, we have published:
Adaptable Security in Wireless Sensor Networks by Using Reconfigurable ECC Hardware Coprocessors, J. Portilla, A. Otero, E. de la Torre, T. Riesgo, O. Stecklina, S. Peter, and P. Langendörfer. International Journal of Distributed Sensor Networks . Hindawi Publishing Corporation. Volume 2010, Article ID 740823, 12 pages. doi:10.1155/2010/740823 PDF
Using SRAM Based FPGAs for Power-Aware High Performance Wireless Sensor Networks, J. Valverde , A. Otero , M. Lombardo, J. Portilla , E. De La Torre, T.Riesgo. Submitted to special issue: Microprocessors and System-on-Chip. Sensors. MDPI AG. PDF
Run-time Scalable Architecture for Deblocking Filtering in H.264/AVC and SVC Video Codecs. Chapter included in the Book: “Embedded Systems Design with FPGAs“, Edited by P. Athanas, D. Pnevmatikatos and N. Sklavos, to appear in Springer with ISBN: 978-1-4614-1361-5, 2012. To be published.