Digital Embedded Systems Publications List

The publications within the digital embedded systems area are divided in the three sub-lines below:

PhD thesis, Master Thesis and Final degree projects

JOURNALS

  • Wireless Sensor Network for Environmental Monitoring: Application in a Coffee Factory, J. Valverde, V. Rosello, G. Mujica, J. Portilla, T. Riesgo, International Journal of Distributed Sensor Networks, 10.1155/2012/638067, pp. 1-18, vol. 2012, issue ID 638067, 2012
  • Using SRAM Based FPGAs for Power-Aware High Performance Wireless Sensor Networks, J. Valverde, A. Otero, M. Lopez, J. Portilla, E. de la Torre, T. Riesgo, Sensors, 10.3390/s120302667, pp. 2667-2692, vol. 12, issue 2012, February 2012
  • Accelerating FPGA-based Evolution of Wavelet Transform Filters by Optimized Task Scheduling, R. Salvador, A. Vidal, F. Moreno, T. Riesgo, L. Sekanina, Microprocessors and Microsystems, 10.1016/j.micpro.2012.02.002, pp. 427-438, issue 36, June 2012
  • Comparison of Phase-shifters for Multiphase Power Converters, A. de Castro, O. Garcia, P. Zumel, T. Riesgo, G. González de Rivera, IETE Journal of Researc, pp. 42-48, vol. 57, issue 1, February 2011
  • Evolutionary Approach to Improve Wavelet Transforms for Image Compression in Embedded Systems, Rubén Salvador, Félix Moreno, Teresa Riesgo, and Lukáš Sekanina, EURASIP Journal on Advances in Signal Processing, 10.1155/2011/97380, pp. 1-20, vol. ID 973806, July 2011
  • Embedded Run-time Reconfigurable Nodes for Wireless Sensor Networks Applications, Y. Esteves Krasteva, J. Portilla, E. de la Torre, T. Riesgo, IEEE Sensor Journal, 10.1109/JSEN.2011.2104948, pp. 1800-1810, vol. 11, issue 9, September 2011
  • Reconfigurable Networks on Chip. DRNoC Architecture, Y.E. Krasteva, E. de la Torre, T. Riesgo, Journal of Systems Architecture, doi:10.1016/j.sysarc.2010.04.003, pp. 293-302, vol. 56, issue 7, July 2010
  • Adaptable Security in Wireless Sensor Networks by Using Reconfigurable ECC Hardware Coprocessors, J. Portilla, A. Otero, E. de la Torre, T. Riesgo, O. Stecklina, S. Peter, and P. Langendörfer, International Journal of Distributed Sensor Networks, 10.1155/2010/740823, pp. 1-12, vol. Article ID 740823, November 2010
  • Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Leve, F. Machado, Y. Torroja, and T. Riesgo, Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, Lecture Notes in Computer Science, 10.1007/978-3-540-95948-9, pp. 399-408, January 2009
  • Power estimation technique for DSP architectures, Y.A. Durrani, T. Riesgo, Digital Signal Processing (Elsevier), 10.1016/j.dsp.2008.09.005, pp. 213-219, vol. 19, issue 2, March 2009
  • Reconfigurable hardware architecture of a shape recognition system based on specialized tiny neural networks with online training, F. Moreno, J. Alarcón, R. Salvador, T. Riesgo, IEEE Transactions on Industrial Electronics, vol. 56, issue 8, August 2009
  • A Piezoelectric minirheometer for measuring the viscosity of polymer microsamples, A.M. Sánchez, R. Prieto, M. Laso, T. Riesgo, IEEE Transactions on Industrial Electronics, pp. 427-436, vol. 55, January 2008
  • Control of Distributed Uninterruptible Power Supply Systems, J.M. Guerrero, L. Hang, J. Uceda, IEEE Transactions on Industrial Electronics, 10.1109/TIE.2008.924173, pp. 2845-2859, vol. 55, issue 8, August 2008
  • A Binary Decision Diagram Structure for Probabilistic Switching Activity Estimation , Felipe Machado, Yago Torroja, and Teresa Riesgo, Journal of Low Power Electronic, pp. 247–262, vol. 4, issue 3, December 2008
  • Rapid prototyping for multi-application sensor networking, J. Portilla, A. de Castro, A. Abrio, T. Riesgo, SPIE Newsroom, 10.117/2.1200708.0851, 2007
  • A digital system to emulate wireless networks, E. Peña, E. de la Torre, A. de Castro, T. Riesgo, Computers & Digital Techniques, IET, 10.1049/iet-cdt:20060055, pp. 444-450, vol. 1, issue 5, September 2007
  • Embedded architecture enables intelligent vehicles, I. López, R. Salvador, J. Alarcón, F. Moreno, SPIE Newsroom, 10.1117/2.1200708.0822, September 2007
  • Architectural power analysis for intellectual property-based digital system, Y.A. Durrani, T. Riesgo, Journal of Low Power Electronics, 10.1166/jolpe.2007.143, pp. 271-279, vol. 3, issue 3, December 2007
  • A modular architecture for nodes in wireless sensor networks, J. Portilla, A. de Castro, E. de la Torre, T. Riesgo, Journal of Universal Computer Science, pp. 328-339, vol. 1, issue 3, March 2006
  • Ubiquitous computing and ambient intelligence: new challenges for computing, J. Bravo, X. Alamán, T. Riesgo, Journal of Universal Computer Science, pp. 233-235, vol. 3, March 2006
  • A Method for Switching Activity Analysis of VHDL-RTL Combinatorial Circuits, Felipe Machado, Teresa Riesgo, Yago Torroja, Lecture Notes in Computer Science, September 2006
  • Concurrent and simple digital controller of an AC/DC converter with power factor correction based on an FPGA, A. de Castro; P. Zumel; O. García; T. Riesgo; J. Uceda, IEEE Transactions on Power Electronics, pp. 334 – 343, vol. 18, issue 1, January 2003
  • Digital control in multi-phase DC-DC converters, A. de Castro; P. Zumel; O. García; T. Riesgo, EPE Journa, pp. 21-27, vol. 13, issue 2, May 2003
  • Design methodologies based on hardware description languages, T. Riesgo; Y. Torroja; E. de la Torre, IEEE Transactions on Industrial Electronics, pp. 3-12, vol. 46, issue 1, February 1999
  • Embedded systems, T. Riesgo, vol. 4, April 1995
  • The user viewpoint. ESA VHDL Modelling Guidelines: An user perspective, T. Riesgo, ECS, vol. 4, April 1995
  • PRENDA: PRoyecto para la Especificación y Normalización en el Diseño de ASICs, Y. Torroja, PCIM Europe Magazin, October 1994
  • Test en VHDL, T. Riesgo; J. Uceda, Journal of Circuits, Systems and Computer, pp. 112-113, November 1994

CONFERENCES

2012

  • “Wake-up architecture for Wireless sensor nodes based on ultra low power FPGA”, V. Rosello, J. Portilla, T. Riesgo, European Conference on Wireless Sensor Networks (EWSN), Trento (Italy), February 2012, ISBN: 978-3-642-28168-6 .
  • “A Novel Method for Radio Propagation Simulation Based on Automatic 3D Environment Reconstruction”, D. He, G. Liang, J. Portilla, T. Riesgo, European Conference on Antennas and Propagation (EuCAP), Prague (Czech Republic), March 2012.
  • “A Hardware In The Loop Design Methodology For FPGA System And Its Application To Complex Functions”, G. Liang, D. He, Jorge Portilla, T. Riesgo, VLSI, Design, Automation and Test (VLSI-DAT ), Hsinchu (Taiwan), April 2012.

2011

  • “Bio-inspired FPGA Architecture for Self-Calibration of an Image Compression Core based on Wavelet Transforms in Embedded Systems”, R. Salvador, A. Vidal, F. Moreno, T. Riesgo, L. Sekanina, Microtechnologies for the New Millennium 2011, pp. 8067_04.1-13, Prague, Czech Republic, April 2011, ISBN: 84-9650-274-0 .
  • “Cost and energy efficient reconfigurable embedded platform using Spartan-6 FPGAs”, A. Otero, M.Llinás, Miguel L. Lombardo, Jorge Portilla, E. de la Torre y T. Riesgo, Microtechnologies for the New Millennium 2011, pp. 8067_06.1-13, Prague, Czech Republic, April 2011, ISBN: 84-9650-274-0 .
  • “Low-power, high-speed FFT processor for MB-OFDM UWB application”, G. Liang, D. He, E. de la Torre, T. Riesgo, Microtechnologies for the New Millennium 2011, pp. 8067_0E.1-13, Prague, Czech Republic, April 2011, ISBN: 84-9650-274-0 .
  • “SCA security verification on wireless sensor network node”, W. He, C. Pizarro, E. de la Torre, J. Portilla, T. Riesgo, Microtechnologies for the New Millennium 2011, pp. 8067_0W.1-15, Prague, Czech Republic, April 2011, ISBN: 84-9650-274-0 .
  • “Scalable 2D architecture for H.264 SVC deblocking filter with reconfiguration capabilities for on-demand adaptation”, T. Cervero, A. Otero, E. de la Torre, S. López, G.M. Callicó, T. Riesgo, R. Sarmiento, Microtechnologies for the New Millennium 2011, pp. 8067_0K.1-13, Prague, Czech Republic, April 2011, ISBN: 84-9650-274-0 .
  • “A Fast Reconfigurable 2D HW Core Architecture on FPGAs for Evolvable Self- Adaptive Systems”, A. Otero, R. Salvador, J. Mora, E.D. Torre, T. Riesgo, and L. Sekanina, NASA/ESA Conference on Adaptive Hardware and Systems (AHS), pp. 336-343, San Diego (California, USA), June 2011, ISBN: 978-1-4577-0598-4 .
  • “Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support”, R. Salvador, A. Otero, J. Mora, E. de la Torre, T. Riesgo, and L. Sekanina, NASA/ESA Conference on Adaptive Hardware and Systems (AHS), pp. 184-191, San Diego (California, USA), June 2011, ISBN: 978-1-4577-0598-4 .
  • “A Novel Scalable Deblocking-Filter Architecture for H.264/AVC and SVC Video Codecs”, T. Cervero, A. Otero, S. Lopez, E. De La Torre, R. Sarmiento, T. Riesgo, G. Callicó, International Conference on Multimedia and Expo Barcelona (ICME), Barcelona (Spain), July 2011.
  • “Framework adaptable y reconfigurable dinámicamente para procesamiento de vídeo: aplicación a la etapa de filtrado adaptativo en sistemas de compresión de vídeo H.264/AVC y SVC”, Cervero, T., Otero A., De la Torre, E., López, S., Callicó G., Riesgo, T. and Sarmiento R, Jornadas de Computación Reconfigurable y Arquitecturas (JCRA), , La Laguna (Tenerife, Spain), September 2011.
  • “Run-time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs”, A. Otero, T. Cervero, E. De La Torre, S. López, G. Callicó, T. Riesgo, R. Sarmiento, International Conference on Field Programmable Logic and Applications (FPL ), Crete (Greece), September 2011.
  • “De la reconfigurabilidad a las redes de sensores (y viceversa)”, T. Riesgo, E. de la Torre, Y. Torroja, J. Portilla, F. Moreno, II Jornadas de Computación Empotrada, Granada (Spain), October 2011.
  • “Improving target localization accuracy of wireless visual sensor networks”, Li Wei, J. Portilla, F. Moreno, T. Riesgo, G. Liang, Annual Conference of the IEEE Industrial Electronics Society (IECON), Melbourne (Australia), November 2011, ISBN: 978-1-61284-971-3 .
  • “The DLMT. An alternative to the DCT”, F. Moreno, D. Aledo, Annual Conference of the IEEE Industrial Electronics Society (IECON), pp. 2192-2197, Melbourne (Australia), November 2011, ISBN: 978-1-61284-971-3 .
  • “Ultra Low Power FPGA-Based Architecture for Wake-up Radio in Wireless Sensor Networks”, V. Roselló, J. Portilla, T. Riesgo, Annual Conference of the IEEE Industrial Electronics Society (IECON), Melbourne (Australia), November 2011, ISBN: 978-1-61284-971-3 .
  • “Wake up Radio Architecture for Wireless Sensor Networks Using an Ultra Low Power FPGA”, V. Roselló, J. Portilla, T. Riesgo, Design of Circuits and Integrated Systems Conference (DCIS), Grande Real Santa EulÁlia, Albufeira (Portugal), November 2011.
  • “2D Reconfigurable Systolic Core Architecture for Evolvable Systems”, A. Otero, R. Salvador, J. Mora, E. de la Torre, T. Riesgo, L. Sekanina, International Conference on ReConFigurable Computing and FPGAs (ReConFig), pp. 327-332, Cancun (México), December 2011, ISBN: 978-0-7695-4551-6 .
  • “A Precharge-Absorbed DPL Logic for Reducing Early Propagation Effects on FPGA Implementations”, W. He, E. de la Torre, T. Riesgo, International Conference on ReConFigurable Computing and FPGAs (ReConFig), pp. 217-222, Cancun (México), December 2011, ISBN: 978-0-7695-4551-6 .
  • “Fault Tolerance Analysis and Self-Healing Strategy of Autonomous, Evolvable Hardware Systems”, R. Salvador, A. Otero, J. Mora, E. de la Torre, L. Sekanina, T. Riesgo, International Conference on ReConFigurable Computing and FPGAs (ReConFig), pp. 164-169, Cancun (México), December 2011, ISBN: 978-0-7695-4551-6 .

2010

  • “Generic Systolic Array for Run-time Scalable Cores”, José Andrés Otero Marnotes, Yana E.Krasteva, Eduardo De la Torre Arnanz and Teresa Riesgo Alcaide, International Symposium on Applied Reconfigurable Computing (ARC), pp. 4-16, Bangkok (Thailand), March 2010.
  • “Development of an aeronautical electromechanical actuator with real time health monitoring capability”, E. de la Torre, A. isturiz, J. Viñals, S. Fernández, R. Basagoiti, J. Novo, International Conference on Recent Advances in Aerospace Actuation Systems and Components Recent Advances in Aerospace Actuation Systems and Component (R3ASC), Toulouse (France), May 2010.
  • “Evolutionary design and optimization of Wavelet Transforms for image compression in embedded systems”, Rubén Salvador, Félix Moreno, Teresa Riesgo and Lukas Sekanina, NASA/ESA Conference on Adaptive Hardware and Systems (AHS), pp. 171, Anaheim (California, USA), June 2010.
  • “A Modular Peripheral to Support Self‐Reconfiguration in SoCs”, Otero Marnotes, Andrés; Morales Cas, Ángel; Portilla, Jorge; De la Torre, Eduardo; Riesgo, Teresa, Euromicro Conference On Digital System Desig (DSD), pp. 88, Lille (France), September 2010.
  • “High level validation of an optimization algorithm for the implementation of adaptive Wavelet Transforms in FPGAs”, Rubén Salvador, Félix Moreno, Teresa Riesgo and Lukas Sekanina, Euromicro Conference On Digital System Desig (DSD), pp. 96 – 103, Lille (France), September 2010.
  • “Run-time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs”, Andrés Otero, Yana E.Krasteva, Eduardo de la Torre, Teresa Riesgo, International Conference Field Programmable Logic and Applications (FPL), pp. 1946-1488, Milán (Italy), September 2010.
  • “Feasibility of HW genetic algorithms for profile selection in reconfigurable autonomous embedded systems”, R. Pujo, A. Otero, E. de la Torre, T. Riesgo, Design of Circuits and Integrated Systems Conference (DCIS), Lanzarote (Canarias, Spain), November 2010.
  • “Implementation of bio-inspired adaptive wavelet transforms in FPGAs. Modeling, validation and profiling of the algorithm”, R. Salvador, F. Moreno, T. Riesgo and L. Sekanina, Design of Circuits and Integrated Systems Conference (DCIS), Lanzarote (Canarias, Spain), November 2010.
  • “Wireless Sensor Network Application for Environmental Impact Analysis and Control”, J. Portilla, J. Valverde, T. Riesgo, Design of Circuits and Integrated Systems Conference (DCIS), Lanzarote (Canarias, Spain), November 2010.

2011

  • “Approach to an FPGA embedded, autonomous object recognition system: run-time learning and adaptation”, R. Salvador, C. Terleira, F. Moreno, T. Riesgo, SPIE Europe conference, Dresden (Germany), May 2009.
  • “Method for run time hardware code profiling for algorithm acceleration”, V. Matev, E. de la Torre, T. Riesgo, SPIE Europe conference, Dresden (Germany), May 2009.
  • “Mission Profile Based Optimization of a Synchronous-Buck DC-DC Converter for a Wearable Power System”, M. Vasić, S. D. Round, J. Biela, J. W. Kolar, International Power Electronics and Motion Control Conference (IPEMC), China, May 2009.
  • “NoC generation of an optimal memory distribution for multimedia systems”, F. Tobajas, V de Armas. E. de la Torre, T. Riesgo, R. Sarmiento, SPIE Europe conference, Dresden (Germany), May 2009.
  • “Using Partial Reconfiguration for SoC Design and Implementation”, Y. Krasteva, F. Tobajas, Jorge Portilla, E. de la Torre, SPIE Europe conference, Dresden (Germany), May 2009.
  • “Secure, Mobile Visual Sensor Networks Architecture”, T. Riesgo, L. Redondo. E. Ladis, et al., IEEE Communications Society Conference on Sensor, Mesh and Ad Hoc Communications and Networks Workshops (SECON Workshop), Rome (Italy), June 2009, ISBN: 1-4244-0830-6 .
  • “Reconfiguring Crypto Hardware Accelerators on Wireless Sensor Nodes”, S. Peter, O. Stecklina, J. Portilla, E. Torre, P. Langendoerfer and T. Riesgo, IEEE Communications Society Conference on Sensor, Mesh and Ad Hoc Communications and Networks Workshops (SECON Workshop), Roma (Italy), July 2009.
  • “Wireless Sensor Network Modular Node Modeling and Simulation with VisualSense”, V. Rosello, J. Portilla, Y. Esteves, T. Riesgo, IEEE Industrial Electronics Control and Instrumentation (IECON), Porto (Portugal), November 2009, ISBN: DOI: 10.1109/ECCE.2010.5618313

2008

  • “Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level”, Felipe Machado, Teresa Riesgo, Yago Torroja, Power And Timing Modeling, Optimization and Simulation (PATMOS), Lisboa, Portugal, september 2008.
  • “A BDD proposal for Probabilistic Switching Activity Estimation”, F. Machado, Y. Torroja, T. Riesgo, Design of Circuits and Integrated Systems Conference (DCIS), Grenoble (France), November 2008, ISBN: 978-2-84813-124-5 .
  • “Feasibility of HW genetic algorithms for profile selection in reconfigurable autonomous embedded systems”, Remi Pujo, Andrés Otero, Eduardo de la Torre, Teresa Riesgo, Design of Circuits and Integrated Systems Conference (DCIS), Grenoble (France), November 2008, ISBN: 978-2-84813-124-5 .
  • “FPGA implementation of an image recognition system based on tiny neural networks and on-line reconfiguration”, F. Moreno, J. Alarcón, R. Salvador, T. Riesgo, IEEE Industrial Electronics Control and Instrumentation (IECON), Orlando, Florida (USA), November 2008, ISBN: 978-1-4244-1766-7 .
  • “NoC Emulation based on Partial Reconfiguration”, Y. E. Krasteva, F. Criado, E. de la Torre, T. Riesgo, Design of Circuits and Integrated Systems Conference (DCIS), Grenoble (France), November 2008, ISBN: 978-2-84813-124-5 .
  • “Remote HW-SW Reconfigurable Wireless Sensor Nodes”, Y.E. Krasteva, J. Portilla, J. M. Carnicer, E. de la Torre and T. Riesgo, IEEE Industrial Electronics Control and Instrumentation (IECON), Orlando, Florida (USA), November 2008, ISBN: 978-1-4244-1766-7 .
  • “Virtual Architectures for Partial Runtime Reconfigurable Systems. Application to Network on Chip based SoC Emulation”, Y.E. Krasteva, E. de la Torre and T. Riesgo, IEEE Industrial Electronics Control and Instrumentation (IECON), Orlando, Florida (USA), November 2008, ISBN: 978-1-4244-1766-7 DOI: 10.1109/ECCE.2010.5618340
  • “Wireless Sensor Networks Node with Remote HW/SW Reconfiguration Capabilities”, J. Portilla, Y. E. Krasteva, J.M. Carnicer, T. Riesgo, Design of Circuits and Integrated Systems Conference (DCIS), Grenoble (France), November 2008, ISBN: 978-2-84813-124-5 .
  • “A Fast Emulation-Based NoC Prototyping Framework”, Y.E. Krasteva, Francisco Criado, Eduardo de la Torre and Teresa Riesgo, International Conference on ReConFigurable Computing and FPGAs (ReConFig), pp. 211-216, Cancun (Mexico), December 2008, ISBN: 978-0-7695-3474-9. .

2007

  • “A Reconfigurable FPGA-Based Architecture for Modular Nodes in Wireless Sensor Networks”, J. Portilla, A. de Castro, T. Riesgo, Southern conference on programmable logic (SPL), Mar de Plata (Argentina), February 2007.
  • “Towards fine and medium grain dynamic functional extraction for hw/sw acceleration”, V. Matev, E. de la Torre,T. Riesgo, Southern conference on programmable logic (SPL), Mar de Plata (Argentina), February 2007.
  • “Architectural design for a low-cost FPGA-based traffic signal detection system in vehicles”, I. López, R. Salvador, J. Alarcón, F. Moreno, SPIE European Symposium on Microtechnologies for the New Millennium, Gran Canaria (Spain), May 2007, ISBN: 97-808-19467-18-8 .
  • “Efficient power macromodeling technique for IP-based digital systems”, Y.A. Durrani, A. Abril, T. Riesgo, IEEE International Symposium on Circuits and Systems (ISCAS), New Orleans (USA), May 2007, ISBN: 1-4244-0921-7 .
  • “High level power estimation for digital system”, Yaseer A. Durrani, Ana Abril, T. Riesgo, SPIE European Symposium on Microtechnologies for the New Millennium, Gran Canaria (Spain), May 2007, ISBN: 97-808-19467-18-8 .
  • “Integrated hardware interfaces for modular sensor networks”, J. Portilla, A. Abril, A. de Castro, T. Riesgo, SPIE European Symposium on Microtechnologies for the New Millennium, pp. 6590 14, Gran Canaria (Spain), May 2007, ISBN: 97-808-19467-18-8 .
  • “Reconfigurable Heterogeneous Communications and Core Reallocation for Dynamic HW Task Management”, Y.E. Krasteva, Eduardo de la Torre, Teresa Riesgo, IEEE International Symposium on Circuits and Systems (ISCAS), New Orleans (USA), May 2007, ISBN: 1-4244-0921-7 .
  • “Architectural power estimation technique for IP-based System-on-Chip”, Y.A. Durrani, A. Abril, T. Riesgo, IEEE International Symposium on Industrial Electronics (ISIE), Vigo (Spain), June 2007.
  • “From Cognitive Architectures: A low-cost FPGA-based design experience”, I. López, R. Sanz. F. Moreno, R. Salvador, J. Alarcón, IEEE International Symposium on Intelligent Signal Processing (WISP), pp. 499-504, Alcalá de Henares-Madrid (Spain), October 2007.
  • “Creating partially reconfigurable systems”, Y. Esteves, E. de la Torre, T. Riesgo, Design of Circuits and Integrated Systems Conference (DCIS), Sevilla (spain), November 2007.
  • “Space Design Exploration of a Viterbi-based ECC Encoding/Decoding Scheme by Wireless Transmission Emulation “, E. Peña, A. González, E. de la Torre, T. Riesgo, Design of Circuits and Integrated Systems Conference (DCIS), Sevilla (Spain), November 2007.
  • “Using wireless sensor networks for an interactive musical application”, J. Portilla, E. Esteban, J. Alcázar, A. Abril, Y. Torroja, T. Riesgo, Design of Circuits and Integrated Systems Conference (DCIS), Sevilla (Spain), November 2007.

2006

  • “Modular Architecture for Wireless Sensor Network Nodes”, J. Portilla, A. de Castro, E. de la Torre, T. Riesgo, Fifth Internacional Conference on Information Processing in Sensor Networks (IPSN), Nashville, Tennessee (USA), April 2006.
  • “Statistical power estimation for register transfer level”, Yaseer A. Durrani, T. Riesgo, F. Machado, International Conference on Mixed Design of Integrated Circuits and Systems, pp. 522-527, Gdynia (Poland), June 2006.
  • “Partial Reconfiguration for Core Reallocation and Flexible Communications”, Y. E. Krasteva, E. de la Torre, Teresa Riesgo, International Workshop on Reconfigurable Communication-Centric System-on-Chips, Montpellier (France), July 2006.
  • “Partial Reconfiguration for Core Reallocation and Flexible Communications”, Y.E. Krasteva, Eduardo de la Torre, Teresa Riesgo, International Workshop on Reconfigurable Communication-Centric System-on-Chips, Montpellier (France), July 2006.
  • “Power macromodeling for high level power estimation”, Y.A. Durrani, T. Riesgo, Workshop on Reconfigurable Communication-Centric System on Chips, pp. 232-236, Montpellier (France), July 2006.
  • “Upcoming challenges for future reconfigurable systems: Architectures, programming tools and technologies (Panel session)”, E. de la Torre, International Workshop on Reconfigurable Communication-Centric System-on-Chips, Montpellier (France), July 2006.
  • “Power estimation for register transfer level by genetic algorithm”, Yaseer A. Durrani, T. Riesgo, F. Machado, International Conference on Informatics in Control Automation and Robotics, pp. 527-530, Setubal (Portugal), August 2006.
  • “A Method for Switching Activity Analysis of VHDL-RTL Combinatorial Circuits”, Felipe Machado, Teresa Riesgo, Yago Torroja, International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS), pp. 645-657. Volume: 4148/2006, Montpellier, Francia, September 2006, ISBN: 978-3-540-39094-7 .
  • “High level statistical power estimation”, Y.A. Durrani, T. Riesgo, International Workshop on Symbolyc Method and Applications to Circuit Design, Firenze (Italy), October 2006.
  • “A VHDL Library for Sensors/Actuators in Sensor Networks”, J. Portilla, J.L. Buron, A. de Castro, T. Riesgo, Design of Circuits and Integrated Systems Conference (DCIS), Barcelona (Spain), November 2006.
  • “An Activity Estimation Tool for VHDL-RTL Combinational Circuits”, F. Machado, A. Abril, Y. Torroja, T. Riesgo, Design of Circuits and Integrated Systems Conference (DCIS), Barcelona (Spain), November 2006.
  • “Applying Partial Reconfiguration for Debugging and Monitoring FPGA based Reconfigurable Systems”, Y. Krasteva, E. de la Torre, T. Riesgo, Design of Circuits and Integrated Systems Conference (DCIS), Barcelona (Spain), November 2006.
  • “Power macromodelling technique for IP-based systems”, Y.A. Durrani, T. Riesgo, A. Abril, Design of Circuits and Integrated Systems Conference (DCIS), Barcelona (Spain), November 2006.
  • “Power estimation for IP-based modules”, Yaseer A. Durrani, T. Riesgo, International Symposium on System-on-Chip, Tampere (Finland), November 2006.
  • “Power macromodelling technique for IP-based systems”, Y. A. Durrani, T. Riesgo, A. Abril, Design of Circuits and Integrated Systems Conference (DCIS), Barcelona (Spain), November 2006.
  • “Statistical power estimation for IP-based design”, Y. A. Durrani, T. Riesgo, IEEE Industrial Electronics Control and Instrumentation (IECON), pp. 4935-4939, Paris (France), November 2006, ISBN: 1-4244-0136-4 .
  • “A Hardware Library for Sensors/Actuators in Sensor Networks”, J. Portilla, J. L. Buron, A. de Castro, T. Riesgo, IEEE International Conference on Electronics, Circuits and Systems (ICECS), Nice (France), December 2006, ISBN: 1-4244-0395-2 .
  • “Power macromodeling for IP modules”, Y. A. Durrani, T. Riesgo, IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 1172-1175, Nice (France), December 2006, ISBN: 1-4244-0395-2 .

2005

  • “A functional validation methodology based on error models for measuring the quality of digital integratted circuits”, C. López; L. Entrena; T. Riesgo; J. Uceda, SPIE: VLSI Circuits and Systems II, pp. 730-741, Sevilla (Spain), May 2005, ISBN: 0-8194-5832-5 DOI: 10.1109/APEC.2011.5744602
  • “Integrated cifcuit debur through FPGA emulation. Application to a PIC-18 macrocell”, M. García; E. de la Torre; F. Casado; L. Entrena; T. Riesgo, SPIE: VLSI Circuits and Systems II, pp. 862-871, Sevilla (Spain), May 2005, ISBN: 0-8194-5832-5 DOI: 10.1109/APEC.2011.5744602
  • “Flexible Core reallocation for Virtex II structures”, Y. Krasteva; A.B. Jimeno; E. de la Torre; T. Riesgo, International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), pp. 189-195, Las Vegas (USA), June 2005, ISBN: 1-932415-74-2 .
  • “Straight method for reallocation of complex cores by dynamic reconfiguration in virtex II FPGAs”, Y.E. Krasteva, A.B. Jimeno, E. de la Torre, T. Riesgo, Internationatal Workshop on Rapid System Prototyping (RSP), pp. 77-83, Montreal (Canada), June 2005, ISBN: 0-7695-2361-7 .
  • “Exploiting VHDL-RTL fetarues to reduce the complexity of power estimation in combinational circuits”, F. Machado; Y. Torroja; T. Riesgo, PRIME-EPFL, Lausana (Suiza), July 2005.
  • “An Approach to Smart Sensor Network Nodes for Distributed Measurement and Control”, J. Portilla: A. de Castro; T. Riesgo, Ubiquitiuous Computing and Ambient Intelligence (UCAml), pp. 87-93, Granada (Spain), September 2005, ISBN: 84-609-9891-X .
  • “ENAMORADO:Una experiencia hacia los terminales móviles reconfigurables en entornos multimedia”, X. Peña; Y. Krasteva; A.B. Jimeno; E. de la Torre;T. Riesgo, Ubiquitiuous Computing and Ambient Intelligence (UCAml), pp. 218-224, Granada (Spain), September 2005, ISBN: 84-609-9891-X .
  • “ENAMORADO: Enabling Nomadic Agents in a Multimedia ORiented Architecture of Distributed Objects”, Y. Krasteva; C. Papagianni ; et. al, eChallenges, Ljubljana (Eslovenia), October 2005.
  • “A Digital System to emulate Wireless Networks”, E. Peña, E. de la Torre, A. de Castro, T. Riesgo, Design of Circuits and Integrated Systems Conference (DCIS), Lisboa (Portugal), November 2005, ISBN: 972-99387-2-5 .
  • “Modular Architecture for Smart Sensor Network Nodes”, J. Portilla, A. de Castro, E. de la Torre, T. Riesgo, Design of Circuits and Integrated Systems Conference (DCIS), Lisboa (Portugal), November 2005, ISBN: 972-99387-2-5 .
  • “Teaching embedded systems and microcontrollers using scale models”, Torroja, Y.; Garcia, O.; Riesgo, T.; de la Torre, E.;, IEEE Industrial Electronics Control and Instrumentation (IECON), pp. 2180 – 2183, Raleigh (USA), November 2005.
  • “Switching Activity Propagation of VHDL-RTL Combinational Designs through an Automated Tool.”, F. Machado, T. Riesgo, Y. Torroja, IEEE International Conference on Electronics, Circuits and Systems (ICECS), Gammarth (Túnez), December 2005.

2004

  • “A methodology to design custom hardware digital controllers for switching power converters”, A. de Castro; T. Riesgo; O. García; J. Uceda, IEEE Power Electronics Specialists Conference (PESC), Aachen (Germany), June 2004, ISBN: 0-7803-8399-0 .
  • “Hardware and software debugging of FPGA based microprocessor systems through debug logic insertion”, M. García; E. de la Torre; Ariza, E.; T. Riesgo, Field Programmable Logic, Antwerpen (Belgium), August 2004.

2003

  • “ENAMORADO: Reconfiguración Parcial de FPGAs en dispositivos móviles”, A. Jimeno, Y. Krasteva, E. de la Torre, T. Riesgo, Jornadas sobre Computación Reconfigurable y Aplicaciones (JCRA), Madrid (Spain), September 2003.
  • “Comparing VHDL and VHDL-AMS for Modelling and Simulation of Power Converters with Digital Control”, A. de Castro; T. Riesgo; O. García; R. Prieto, Design of Circuits and Integrated Systems Conference (DCIS), Ciudad Real (Spain), October 2003, ISBN: 84-87087-40-X .

2002

  • “Concurrent and simple digital controller of an AC/DC converter with power factor correction”, P. Zumel; A. de Castro; O. García; T. Riesgo; J. Uceda, IEEE Applied Power Electronics Conference and Exposition (APEC), pp. 469 – 475 vol.1, Dallas (EEUU), March 2002, ISBN: 0-7803-7404-5 .
  • “A Modular Environment for Learning Digital Control Applications”, Y. Torroja; R. Velasco; E. Angulo; T. Riesgo; E. de la Torre, European Workshop on Microelectronics Education (EWME), Vigo (Spain), May 2002.
  • “A system-on chip for Smart sensors”, A. de Castro; J.M. Chaquet; E. Morejón; T. Riesgo; J. Uceda,, IEEE International Symposium on Industrial Electronics (ISIE), pp. 595-599 vol. 2, L’Aquila (Italia), July 2002, ISBN: 0-7803-7369-3 DOI: 10.1109/DSD.2010.96
  • “Non-Intrusive Debugging using the JTAG interface of FPGA-Based Prototypes”, E. de la Torre; M. García; T. Riesgo; Y. Torroja; J. Uceda, IEEE International Symposium on Industrial Electronics (ISIE), pp. 666-671 vol. 2, L’Aquila (Italia), July 2002, ISBN: 0-7803-7369-3 .
  • “FPGS Debugging through JTAG: Developing highly configurable debug modules”, M. García; E. de la Torre; T. Riesgo; L. Entrena, Design of Circuits and Integrated Systems Conference (DCIS), pp. 125-130, Santander (Spain), October 2002, ISBN: :84-8102-311-6 .
  • “Reusable and reconfigurable system for sensor interfacing and control”, A. de Castro; T. Riesgo; J. Uceda, Design of Circuits and Integrated Systems Conference (DCIS), pp. 213-218, Santander (Spain), October 2002, ISBN: :84-8102-311-6 .
  • “Custom Hardware IEEE 1451.2 Implementation for Smart Transducers”, A. de Castro; T. Riesgo; E. de la Torre; Y. Torroja; J. Uceda, IEEE Industrial Electronics Control and Instrumentation (IECON), Sevilla (Spain), November 2002, ISBN: 0-7803-7474-6 .

2001

  • “Highly configurable solutions for Microprocessor-Bassed Control Boards”, T. Riesgo; E. de la Torre; M. García; A. de Castro; Y. Torroja; J. Uceda, Design, Automation and Test in Europe (DATE), pp. 85-89, Munich (Alemania), March 2001, ISBN: 0 7695-0993-2 .
  • “Mantenimiento de configuraciones y depuración de hardware mediante la herramienta CHDT”, E. de la Torre, M. García, A. de Castro, T. Riesgo, J. Uceda, Jornadas sobre Computación Reconfigurable y Aplicaciones (JCRA), pp. 217-224, Alicante (Spain), September 2001.
  • “A simple digital hardware to control a PFC converter”, P. Zumel; A. de Castro; O. García; T. Riesgo; J. Uceda, IEEE Industrial Electronics Control and Instrumentation (IECON), pp. 943 – 948 vol.2,, November 2001, ISBN: 0-7803-7108-9 .
  • “Debugging and Tracing in JTAG-Compatible FPGA-Based Designs”, M. Garcia; A. de Castro; E. de la Torre; T. Riesgo; J. Uceda, Design of Circuits and Integrated Systems Conference (DCIS), Oporto (Portugal), November 2001.
  • “FPGA-based Control of a Flyback Converter with Power Factor Correction”, A. de Castro; P. Zumel; O. García; T. Riesgo; J. Uceda, Design of Circuits and Integrated Systems Conference (DCIS), Oporto (Portugal), November 2001.
  • “Using a simplified hardware model to analyse the quality of VHDL based designs”, Y. Torroja; F. Casado; F. Machado; T. Riesgo; E. de la Torre; J. Uceda, Design, Automation and Test in Europe (DATE), pp. 191-196, Paris (Francia), March 2000, ISBN: 0-7695-0537-6 .
  • “Application of VHDL features for optimization of functional validation quality measurement”, C. López; T. Riesgo; Y. Torroja; J. Uceda, Proceedings of Forum on Design Languages (FDL), pp. 79-87, Tubingen (Alemania), September 2000, ISBN: 3-00-006540-7 .
  • “BACO: Diseño Reutilizable para Bajo Consumo. Aplicación a los Controladores de Periféricos”, L. Entrena; T. Riesgo; J. Uceda, Seminario del Programa Nacional de Tecnologías de la Información y las Comunicaciones TEDEA, Almagro (Ciudad Real), September 2000.
  • “A Set of Hardware Components for a Reconfigurable Control and Communications Board”, F. Casado; F. Machado; T. Riesgo; E. de la Torre; Y. Torroja; J. Uceda, IEEE Industrial Electronics Control and Instrumentation (IECON), pp. 1707-1712 vol. 3, Nagoya (Japón), October 2000, ISBN: 0 7695-0993-2 .
  • “A methodoly to develop configurable control boards supported by the CHDT tool”, A. de Castro; M. García; M. del Real; E. de la Torre; T. Riesgo; J. Uceda, Design of Circuits and Integrated Systems Conference (DCIS), pp. 77-82, Montpellier (Francia), November 2000.
  • “A simple method to estimate the area of VHDL RTL descriptions”, F. Machado; Y. Torroja; F. Casado; T. Riesgo; E. de la Torre; J. Uceda, Design of Circuits and Integrated Systems Conference (DCIS), pp. 212-217, Montpellier (Francia), November 2000.
  • “Application of Fault Simulation Techniques to Design Validation Quality Measurement”, C. López; T. Riesgo; Y. Torroja; J. Uceda; L. Entrena, Design of Circuits and Integrated Systems Conference (DCIS), pp. 415-420, Montpellier (Francia), November 2000.
  • “AVI: A tool to learn VHDL through Internet”, J. Pardo; M. Iriso; T. Riesgo; E. de la Torre; Y. Torroja; J. Uceda, Design of Circuits and Integrated Systems Conference (DCIS), pp. 224-229, Montpellier (Francia), November 2000, ISBN: DOI: 10.1109/DSD.2010.100 10.1109/DSD.2010.100
  • “Design and validation of a set of macrocells for a configurable control board”, F. Casado; F. Machado; T. Riesgo; E. de la Torre; Y. Torroja. J. Uceda, Design of Circuits and Integrated Systems Conference (DCIS), pp. 264-269, Montpellier (Francia), November 2000.

1999

  • “ARDID: A tool for the quality analysis of VHDL based designs”, Y. Torroja; C. López; M. García; T. Riesgo; E. de la Torre; J. Uceda, Forum on Design Languages (FDL), pp. 392-401, Lyon (Francia), September 1999.
  • “A macrocell for CAN interface: design for reuse experience”, M. Quintana; J. de Lucas; T. Riesgo; Y. Torroja; J. Uceda, Design of Circuits and Integrated Systems Conference (DCIS), pp. 269-274, Palma de Mallorca (Spain), November 1999, ISBN: 84-7632-424-3 .
  • “A tool for development and Debug of configurable FPGA-based embedded system prototypes”, M. García; E. de la Torre; T. Riesgo; Y. Torroja; J. Uceda, Design of Circuits and Integrated Systems Conference (DCIS), pp. 619-624, Palma de Mallorca (Spain), November 1999, ISBN: 84-7632-424-3 .
  • “Design of a CAN interface for custom circuits”, J. de Lucas; M. Quintana; T. Riesgo; Y. Torroja; J. Uceda, IEEE Industrial Electronics Control and Instrumentation (IECON), pp. 662-667 vol. 2, San Francisco (USA), November 1999, ISBN: 84-606-8345-7 .

1998

  • “Quality estimation of test vectors and functional validation procedures based on fault and error models”, T. Riesgo; Y. Torroja; E. de la Torre; J. Uceda, Design, Automation and Test in Europe (DATE), pp. 955-956, Paris (Francia), February 1998, ISBN: 0-8186-8359-7 .
  • “An error simulator to estimate the quality of design validations experiments”, C. López; T. Riesgo; Y. Torroja; E. de la Torre; J. Uceda, Forum on Design Languages (FDL), Lausanne (Suiza), September 1998.
  • “A design methodology for the development of a high performance DSP”, Y. Torroja; C. López; J.L. Ruiz; J.L. García; J. Uceda, Design of Circuits and Integrated Systems Conference (DCIS), Madrid (Spain), November 1998, ISBN: 84-606-8345-7 .
  • “A method to perform error simulation in VHDL”, C. López; T. Riesgo; Y. Torroja; E. de la Torre; J. Uceda, Design of Circuits and Integrated Systems Conference (DCIS), pp. 496-501, Madrid (Spain), November 1998, ISBN: 84-606-8345-7 .
  • “A virtual prototype of an FPG. A based rapid prototyping system”, T. Ramírez; E. de la Torre; Y. Torroja; J. Uceda, Design of Circuits and Integrated Systems Conference (DCIS), Madrid (Spain), November 1998, ISBN: 84-606-8345-7 .
  • “An ASIC for satellite on-board control communictions”, C. Alcalá; E. de la Torre; J. Sánchez; J.R. Alonso, Design of Circuits and Integrated Systems Conference (DCIS), Madrid (Spain), November 1998, ISBN: 84-606-8345-7 .

1997

  • “A simplified design approach for constant-frequency single-switch three phase discontinuous boost power factor preregulators”, D. Simonetti; J. Sebastián; J. Uceda, IEEE International Symposium on Industrial Electronics (ISIE), pp. 578-582, Guimaraes (Portugal), 1997.
  • “Estimation of the quality of design validation experiments based on error models”, T. Riesgo; Y. Torroja; C. López; J. Uceda, VHDL International User’s Forum, pp. 83-92, Toledo (Spain), April 1997, ISBN: 84-8102-158-X .
  • “Minimizing PFP converters [power factor preregulators]”, Reis; F.S.D.; J. Sebastián; J. Uceda, IEEE International Telecommunications Energy Conference (INTELEC), pp. 723 – 728,, October 1997.
  • “A configurable VHDL model of FIFO memories”, E. de la Torre; J. de la Fuente; Y. Torroja; T. Riesgo; J. Uceda, Design of Circuits and Integrated Systems Conference (DCIS), pp. 305-309, Sevilla (Spain), November 1997, ISBN: 84-88783-28-0 .
  • “A library of reusable arithmetic components”, P.L. Ruiz; T. Riesgo; Y. Torroja; E. de la Torre; J. Uceda, Design of Circuits and Integrated Systems Conference (DCIS), pp. 559-564, Sevilla (Spain), November 1997, ISBN: 84-88783-28-0 .
  • “A set of tools to help in the VHDL design flow of complex systems”, Y. Torroja; C. López,. T. Riesgo; J. Uceda, Design of Circuits and Integrated Systems Conference (DCIS), pp. 299-304, Sevilla (Spain), November 1997, ISBN: 84-88783-28-0 .
  • “A virtual and a real prototype of a Boundary Scan tester”, E. de la Torre; F. Matías; J.M. Uhagón; J. Uceda, Design of Circuits and Integrated Systems Conference (DCIS), Sevilla (Spain), November 1997, ISBN: 84-88783-28-0 .
  • “Design and prototyping of DSP custom circuits based on a library of arithmetic components”, P.L. Ruiz; T. Riesgo; J. Uceda, IEEE Industrial Electronics Control and Instrumentation (IECON), pp. 191-196, Nueva Orleans (USA), November 1997, ISBN: 0-7803-3932-0 .
  • “Dissemination activities within OMI technology networks”, M. Castro; J.N. Cigarran; C. de Mora; J. Peire; T. Riesgo; J. Uceda, IEEE Industrial Electronics Control and Instrumentation (IECON), pp. 213-217, Nueva Orleans (USA), November 1997, ISBN: 0-7803-3932-0 .

1996

  • “ENERCHIP: ASIC fo power quality measurement and control”, T. Riesgo; J. Uceda; W. Schögler; W. Moshammer; J.L. Ramos; V. Guerreiro, European Design & Test Conference (ED&TC), pp. 71-76, París (Francia), March 1996, ISBN: 0 8186-7423-7 .
  • “The use of standards in electronic design”, T.Riesgo; E. de la Torre; Y. Torroja; J. Uceda, IEEE Industrial Electronics Control and Instrumentation (IECON), pp. 407-412, Taipei (Taiwan), August 1996, ISBN: 0-7803-2775-6 .
  • “A fault model for VHDL descriptions at the register transfer level”, T. Riesgo; J. Uceda, European Design Automation Conference (EURODAC), pp. 462-467, Ginebra (Suiza), September 1996, ISBN: 0-8186-7573-X .
  • “EUROMIC: EURopean OMI centres”, N. Krim; T. Riesgo; P. Lister; K. Hess; P. Pype; T. Gore; J. Peire, Embedded Microprocessor Systems (EMSYS), Berlín (Alemania), September 1996.
  • “Timing optimization by an improved redundancy addition and removal technique”, L.A. Entrena; J.A. Espejo; E. Olías; J. Uceda, European Design Automation Conference (EURODAC), Ginebra (Suiza), September 1996, ISBN: 0-8186-7573-X .
  • “Simplifying the design of a DCM boost PFP”, D.S.L. Simonetti ; J.L.F. Vieira; J. Sebastián; J. Uceda, IEEE International Conference on Power Electronics (CIEP), pp. 138 – 141, Mexico, October 1996, ISBN: DOI: 10.1007/978-3-642-12133-3_4
  • “Generación de modelos VHDL de lógica de test para diseños basados en macroceldas”, E. de la Torre; J. Calvo; J. Uceda, Design of Circuits and Integrated Systems Conference (DCIS), Sitges (Barcelona, Spain), November 1996, ISBN: 84-89349-83-5 .
  • “Método de estimación de la calidad del test desde descripciones VHDL sintetizables”, T. Riesgo; J. Uceda, Design of Circuits and Integrated Systems Conference (DCIS), pp. 613-618, Sitges (Barcelona, Spain), November 1996, ISBN: 84-89349-83-5 .

1995

  • “CAD in Test”, T. Riesgo; E. de la Torre; Y. Torroja; E. Olías; J. Uceda, IEEE International Symposium on Industrial Electronics (ISIE), pp. 33-38, Atena (Greece), July 1995, ISBN: 0-7803-2683-0 .
  • “Sensors for Railways Maintenance”, J.L. Aparicio; E. de la Torre; Y. Torroja; P.L. Castedo; P.M. Martínez, Reunión Nacional de Investigación en el Area Eléctrica, Barcelona (Spain), September 1995.
  • “An improved battery charger/discharger topology with power factor correction”, C. Aguilar; F. Canales; J. Arau; J. Sebastián; J. Uceda, IEEE International Conference on Power Electronics (CIEP), pp. 02-07, Mexico, October 1995.
  • “A resonant high voltage converter with C-type output filter”, C. Blanco Viejo; M.A. Perez Garcia; M. Rico Secades; J. Uceda, IEEE Industrial Electronics Control and Instrumentation (IECON), pp. 2401 – 2407 vol.3, Orlando (Florida, USA), November 1995, ISBN: 0-7803-3026-9 .
  • “A resonant high voltage converter with C-type output filter”, C. Blanco; M.A. Pérez; M. García; J. Uceda, IEEE Industrial Electronics Control and Instrumentation (IECON), Orlando (Florida, USA), November 1995, ISBN: 0-7803-3026-9 .
  • “ENERCHIP: An Integrated Circuit for Power Control”, T. Riesgo; J. Sánchez; W. Schögler; W. Moshammer; V. Guerreiro; J.L. Ramos, IEEE Industrial Electronics Control and Instrumentation (IECON), pp. 662-667, Orlando (Florida, USA), November 1995, ISBN: 0-7803-3026-9 .
  • “An integrated battery charger/discharger with power factor correction”, C. Aguilar; F. Canales; J. Arau; J. Sebastián; J. Uceda, IEEE Power Electronics Specialists Conference (PESC), pp. 714 – 719 vol.2, June 1995, ISBN: 0-7803-2730-6

1994

  • “Design Process Based on Hardware Description Languages”, T. Riesgo; Y. Torroja; J. Uceda, IEEE International Symposium on Industrial Electronics (ISIE), pp. 59-65, Santiago de Chile (Chile), May 1994, ISBN: 0-7803-1961-3 .
  • “An optimized DC-to-DC converter topology for high-voltage pulse-load applications”, V. García; M. Rico; J. Sebastián; M.M. Hernando; J. Uceda, IEEE Power Electronics Specialists Conference (PESC), pp. 1413 – 1421 vol.2, Taipei (Taiwan ROC), June 1994, ISBN: 0-7803-1859-5 .
  • “Study of an optimized resonant converter for high-voltage applications”, V. García; M. Rico; J. Sebastián; M.M. Hernando; J. Uceda, IEEE International Conference on Power Electronics (CIEP), pp. 114 – 121, Mexico, August 1994.
  • “ENERCHIP: Circuito integrado para control energético”, T. Riesgo; J. J. Uceda; L. Ramos; J. Antonio Torres, Design of Circuits and Integrated Systems Conference (DCIS), pp. 491-496, Las Palmas (Spain), November 1994.

1993

  • “A Hardware Oriented Fault Model for Synthesizable Descriptions”, T. Riesgo; J. Uceda, Summaries of North Atlantic Test Workshop, Hannover (New Hampshire, USA), June 1993.
  • “Modeling the ModulatedFrequency Boost AC-DC Preregulator”, D.S.L. Simonetti; J. Sebastián; J. Uceda, IEEE International Conference on Power Electronics (CIEP), Cuernavaca (Mexico), August 1993.
  • “A Dynamic Communication Strategy for the Distributed ATPG System DPLATON”, M.J. Aguado; M.A. Miranda; E. de la Torre; C. López Barrio, European Design Automation Conference (EURODAC), Hamburgo (Alemania), September 1993.
  • “Concurrent Hierarchical Fault Simulation using VHDL”, T. Riesgo; S. Olcoz, VHDL International User’s Forum, pp. 119-130, San José (California, USA), October 1993.
  • “Distributed Implementation of an ATPG System Using Dynamic Fault Allocation”, M.J. Aguado; M.A. Miranda; E. de la Torre; C. López Barrio, International Power Electronics and Motion Control Conference (EPE-PEMC), Baltimore, USA, October 1993.
  • “An Artificial Vision System used for the Measurement of the Overhead Wire in Railway Applications”, Y. Torroja; S. García; J.L. Aparicio; P.M. Martínez, IEEE Industrial Electronics Control and Instrumentation (IECON), Maui (Hawai, USA), November 1993, ISBN: 07803-0891-3 .
  • “High Level Testing for Digital VLSI: A Survey”, T. Riesgo; J. Uceda; F. Aldana, IEEE Industrial Electronics Control and Instrumentation (IECON), pp. 402-407, Maui (Hawai, USA), November 1993, ISBN: 07803-0891-3 .
  • “Fundamentos de la optimización de circuitos digitales mediante adición y eliminación de redundancias”, L. Entrena; J. Uceda Servicio de Publicaciones de la Universidad de Cantabria, Design of Circuits and Integrated Systems Conference (DCIS), Málaga (Spain), December 1993.

1992

  • “A Unified Analysis of Multiresonant Converters”, F. Nuño; J. Sebastián; J. Lopera; J. Díaz, IEEE Power Electronics Specialists Conference (PESC), Toledo (Spain), June 1992.
  • ” Algunos criterios de diseño en circuitos de compresión digital de señal basados en FFT”, T. Riesgo; R. Asensi; J.E. Ortiz; J. Uceda, Design of Circuits and Integrated Systems Conference (DCIS), pp. 471-476, Toledo (Spain), November 1992, ISBN: DOI: 10.1109/DSD.2010.43
  • ” ASIC’s para estación remota”, E. de la Torre; T. Riesgo; J. Uceda; A. Hernández; J. Cabrera, Design of Circuits and Integrated Systems Conference (DCIS), pp. 477-482, Toledo (Spain), November 1992.
  • ” Perspectivas del test de circuitos integrados desde descripciones VHDL”, T. Riesgo; Y. Torroja; E. de la Torre; J. Uceda, Design of Circuits and Integrated Systems Conference (DCIS), pp. 313-318, Toledo (Spain), November 1992.
  • ” Síntesis automática de FSM a partir de descripciones gráficas”, Y. Torroja; E. de la Torre; T. Riesgo; I. Pompa; J. Uceda, Design of Circuits and Integrated Systems Conference (DCIS), pp. 507-508, Toledo (Spain), November 1992.
  • ” Testing VLSI Circuits from VHDL Descriptions”, T. Riesgo; Y. Torroja; E. de la Torre; J. Uceda, IEEE Industrial Electronics Control and Instrumentation (IECON), pp. 1052-1057, San Diego (USA), November 1992, ISBN: 0-7803-0891-3 .

1991

  • “A New Approach on Fault List Handling for Faster Fault Elimination and Direct Test Vector Generation”, M.J. Aguado; J.L. Conesa; E. de la Torre; J. Uceda, Euromicro, Viena (Austria), 1991.
  • “A Comparative Analysis of Different Fault Simulation Techniques for VLSI Circuits Testing”, Y. Torroja; T. Riesgo; E. de la Torre; J. Uceda, IEEE Industrial Electronics Control and Instrumentation (IECON), pp. 1226-1234, Kobe (Japón), November 1991, ISBN: 0-87942-688-8 .
  • “Análisis comparativo de tres técnicas de simulación de fallos”, Y. Torroja; T. Riesgo; E. de la Torre; J. Uceda, Design of Circuits and Integrated Systems Conference (DCIS), pp. 39-44, Santander (Spain), November 1991, ISBN: 84-87412-61-0 .
  • ” Simulación y generación de vectores de test para circuitos integrados mediante el uso de transputers”, E. de la Torre; Y. Torroja; T. Riesgo; J. Uceda, Design of Circuits and Integrated Systems Conference (DCIS), pp. 393-398, Santander (Spain), November 1991, ISBN: 84-87412-61-0 .