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Special Sessions

Authors are invited to submit contributions to the following two confirmed special sessions:

#1 Cutting Edge Heterogeneous Image Processing Systems



Reconfigurable and heterogeneous systems-on-chip open new opportunities for image processing in different areas such as surveillance, industrial vision, big data analytics, medical imaging or vision for robotics. FPGA-based architectures offer more massive computing capabilities than GPPs and their parallel capabilities create huge opportunities for image processing architectures. However, if the introduction of FPGAs can address some performance issues, it introduces new challenges in terms of programmability, hardware abstraction, efficient matching between HW and SW parts, etc.

The motivation for this special session is to bring together researchers working on Reconfigurable architectures and Computer Vision. It provides a unique opportunity to get to know the work and the people researching in the field, and involve a fruitful exchange of ideas.

Publications for this special session may target smart cameras, embedded vision, and architecture for perception in a robotics context.

Key areas include, but are not limited to distributed vision systems, smart intra- or inter-system communication, reconfigurable and heterogeneous computing applied to image processing, as well as new architectures, languages or paradigms for distributed image processing systems.

Demonstrations should focus on the benefits brought by reconfigurability and/or heterogeneity on an image processing system in terms of either speed, load balancing, energy, reliability, approximate computing, fault tolerance, adaptivity, or any other system performance-related property.

#2 High Level Design Methodologies for Reconfigurable Computing and Adaptive Systems: Tool Flows and Applications


  • Rubén Salvador, Research Center on Software Technologies and Multimedia Systems, Universidad Politécnica de Madrid (Spain)
  • Jocelyn Sérot, Institut Pascal, Universite Blaise Pascal (France)
  • Eduardo Juarez, Research Center on Software Technologies and Multimedia Systems, Universidad Politécnica de Madrid (Spain)


During the last years, improved sets of tools and methodologies have hit the arena of reconfigurable system design, which have in turn raised the abstraction level typically used for the specification of reconfigurable systems. This has allowed, besides an increase in designers productivity, to enable the exploration of more complex target applications, the implementation of more intelligent behaviors and the achievement of improved final system performance.

In this line of work, submissions covering different approaches -some more well established than others in the reconfigurable computing community- to system specification and High Level Synthesis strategies such as C/C++, OpenCL, dataflow graphs, etc., are encouraged. Bringing together researchers using different methodologies and tools, exploring different applications and targeting different specific features of the final system, will enable a productive discussion environment for the exchange of ideas that can help boosting upcoming efforts in the field.

Applications might span a broad range of target scenarios like (but not restricted to): high performance computing systems, either embedded or at the cluster/cloud level; hardware accelerators for machine learning/deep learning/artificial intelligence; compute and/or control-intensive cyber physical systems in safety/time-critical applications; self-adaptation (self-awareness, context-awareness, self-reconfiguration, ...) for system reliability, resiliency and graceful degradation in hazardous environments.

Hence, submissions might well address topical system features such as runtime task/parallelism management and HW/SW load balancing, dynamic partial reconfiguration, energy optimization, fault-tolerance and self-healing techniques, approximate computing, dependability, or any other system features that might benefit from the use of these design approaches.

#3 Fault and Security Management in NoCs and MPSoCs



Shrinking feature sizes in manufacturing technologies are the key enabling factor for MPSoCs and at the same time their major limitation, leading to an increased wear-out during the life-time of a product. Therefore systems have to cope with an increasing number of intermittent and permanent faults, requiring efficient built-in fault detection (test) and fault management, including reconfiguration strategies allowing a graceful degradation of the physical elements of a device.

The upscaling of SoCs furthermore raises a lot of security issues, which have to be considered during the design of complex on-chip systems. New attack scenarios need to be analyzed and countermeasures have to be considered during the design of platforms.

In this session novel methods for fault-resilience and security in NoCs and MPSoCs are targeted.