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Marco Platzner (Paderborn University):"Extending Operating System Services over FPGAs"

Date: Wednesday, July 12th

Abstract:The idea of operating systems for FPGAs is around for some 20 years, and evolved from early concepts of hardware paging to more expressive software-centric abstractions that support partial reconfiguration and hardware/software migration. In this talk I will discuss the motivation and approaches for operating system integration of reconfigurable hardware, and then introduce to ReconOS, our open-source operating system for reconfigurable computers that offers a unified multi-threaded programming model for hardware and software threads. By semantically integrating hardware accelerators into a standard operating system environment, ReconOS supports a structured application development process, rapid design space exploration, and the creation of autonomous hybrid multi-core systems.

Bio: Marco Platzner is Professor for Computer Engineering at Paderborn University. Previously, he held research positions at the Computer Engineering and Networks Lab at ETH Zurich, Switzerland, the Computer Systems Lab at Stanford University, USA, the GMD - Research Center for Information Technology (now Fraunhofer IAIS) in Sankt Augustin, Germany, and the Graz University of Technology, Austria. His research interests include reconfigurable computing, hardware-software codesign, and parallel architectures. Marco Platzner holds diploma and PhD degrees in Telematics (Graz University of Technology, 1991 and 1996), and a Habilitation degree for the area hardware-software codesign (ETH Zurich, 2002). Marco Platzner is member of the board of the Paderborn Center for Parallel Computing and the board of the Paderborn Institute of Advanced Studies in Computer Science and Engineering.


Manfred Glesner (Technische Universität Darmstadt):"The rebirth of hardware: Open-source hardware initiatives for IoT- and MINT-based developments"

Date: Wednesday, July 12th

Abstract: Open source software is a well-known topic. Open source hardware is a fairly new one: as we approach the limits of available electronic systems in Silicon, many specific designs in the past moved to generic standard chips. Best example are electronic components like ARDUINO and Raspberry-Pi. In this domain we see an increased offer of high performance boards from companies like INTEL. The offers are extended to sensor and actor systems. There is now an active Hacker-Community which is meeting in many places of the world and offering "hacks" in form of finished designs that can be openly exchanged. The whole development under the term DIY= Do it yourself has led to new offerings and companies (e.g. Adafruit et al) also for printed circuit board design in form of multi-project-realizations (OSH-park initiative). The talk is carefully reviewing the developments in this new area and gives an overview of typical killer applications in IT (= software defined radio), wearables, medical applications and Industry 4.0.

Bio: Prof. em. Dr. Dr.h.c.mult. Manfred Glesner, IEEE Fellow (2000), is head of the microelectronic system research group at Technische Universitaet Darmstadt, Fachbereich Elektrotechnik und Informationstechnik. His research activities are in the areas of embedded systems design, high-level synthesis and physical design, especially for intelligent signal processing in mechatronics and smart systems in general. He was in 1982 the first in Germany to design with students a multiproject chip as part of the regular education. In recent time his focus was on the promotion of MOOC-based education in advanced technologies. He has organised many national and international conferences and is a member of the programme committees of several conferences and workshops. Together with Gilles Sassatelli he is cofounder of the ReCoSoC-Conference Series starting in 2005 in Montpellier. He already successfully supervised 64 PhDs during his career. Prof. Glesner was founder and is one of the leading steering committee member of the European Workshop on Microelectronic Education. In 2007, he received the French Order “Chevalier dans l’Ordre des Palmes Académiques” for his collaborative work with multiple French research institutes. Recently, he received international awards from Estonia (Medal Terra Cross Mariana, 2014) and Mongolia (Kublai-Kahn-Medal, 2009) in recognition of his academic achievements with these countries. Prof. Glesner holds four Honorary Doctorships from the Technical University Tallinn (Estonia, 1996), Bukarest Polytechnic University (Romania, 1997), Mongolian Technical University Ulaanbaatar, (Mongolia, 2009) and the University of Liepaya (Latvia, 2014). Since 2013 Prof. Glesner is a member of the Advisory Board (=Hochschulrat) of the University of Applied Sciences in Dortmund. Further he is also member of the VDE-Rhein-Main advisory board which is actively promoting electrical engineering for the society in Germany. He is a consultant to many national, European and international organizations (IEEE; IFIP et al) and companies. In the last years he supported DAAD (Germany) to build up the GMIT = German Mongolian Institute for Resources and Technology in Nalaikh (Ulaanbaatar, Mongolia) where he was also a DAAD-guest professor in 2016. In recent times he devoted new activities to the promotion of Open-Source-Hardware activities, also for STEM/MINT-education.


Angel Alvaro Sanchez (R&D Manager. Thales Alenia Space Spain):"Space, the final frontier, the best testbed: Applications, Challenges and Needs for the application of reconfigurable SoCs to Space"

Date: Thursday, July 13th

Abstract:The space business is in turmoil, the rise of satellite constellations linked to the fierce evolution of the telecommunication market has changed the rules of a traditionally stable game. In the scientific domain, successes as Rosetta and Cassini-Huygens are making scientists grow bolder and ask for more ambitious missions. This means that satellites and planetary probes are evolving at an accelerated pace towards increased data processing needs, higher flexibility, higher system complexity, reduced cost and higher autonomy. This scenario is a natural application field for ReCoSoCs, that can provide the data processing capability with hardware and firmware flexibility at a reduced cost. But this will only be possible if we are able to make them compliant to the stringent constraints derived from the harsh space environment and strict reliability and dependability requirements, imposed by missions that fly there where no one can go to press a reset button or solder a last minute wire. This lecture will review the current and future needs of the space business in terms of data processing, assessing the applicability of the ReCoSoC devices for scientific, telecommunication or earth observation missions. The particularities of the space environment and the ways SoC reconfiguration and self-awareness can be used to overcome the challenges of radiation and mission reliability shall be presented, as well as the current trends on SoC architectures for space. Finally, the role of the space missions as technological demonstrators and testbeds will be discussed.

Bio:Head of R&D and Systems Project Manager: Telecommunications Engineer (1997) by UPM in Madrid, has more than 20 years of experience in the space sector. Starting at Alcatel Space as a designer of digital equipment where he designed several FPGA based units for the Rosetta and Mars Express Missions. He has been responsible for the digital engineering group and director of operations. In 2009 returns to the technical activity and occupies a position within the R&D Management Area at Thales Alenia Space Spain. In his present position he coordinates the company R&D strategy including both internal R&D as well as the several H2020 projects where Thales Alenia Space Spain is involved.


Leandro Indrusiak (University of York):"Networks-on-Chip for Real-Time and Mixed-Criticality Applications"

Date: Thursday, July 13th

Abstract: Networks-on-Chip (NoC) provide packet-switching infrastructure for multiple types of system-wide communications, such as message passing between tasks running on different cores, data transfers between external memories and local scratchpads, or paging and coherency mechanisms for multi-level caches. In all cases, the performance of the NoC affects system timeliness and thus must be taken into account when analysing application-level real-time guarantees. This is specially true when application tasks and communication packets of different levels of criticality share the NoC infrastructure. This talk will present pros and cons of NoC architectures with priority-preemptive virtual channels, and will show their potential for handling real-time and mixed-criticality traffic. Then, it will review the state-of-the-art in real-time analysis for those NoC architectures, enabling safe upper bounds to end-to-end latency (tasks and packet flows) in single and mixed-criticality applications. Finally, it gives an insight on how real-time analysis can be used as a fitness function in the design space exploration of NoC-based embedded systems, aiming to meet performance guarantees and optimise energy dissipation.

Bio: Leandro Soares Indrusiak graduated in Electrical Engineering from the Federal University of Santa Maria (UFSM, Brazil) and obtained a MSc in Computer Science from the Federal University of Rio Grande do Sul (UFRGS, Brazil) in 1995 and 1998, respectively. He held a tenured assistant professorship at the Informatics department of the Catholic University of Rio Grande do Sul (Brazil) from 1998 to 2000. From 2001 to 2008 he worked as a researcher at the Technische Universitaet Darmstadt (Germany) where he worked towards a PhD and then lead a research team on the area of System-on-Chip design. His binational doctoral degree was jointly awarded by UFRGS and TU Darmstadt in 2003. Since 2008, he is a permanent faculty member of University of York's Computer Science department (Lecturer 2008, Senior Lecturer 2013, Reader 2016), and a member of the Real-Time Systems (RTS) research group. His current research interests include on-chip multiprocessor systems, distributed embedded systems, resource allocation, cloud computing, and real-time networks, having published more than 120 peer-reviewed papers in the main international conferences and journals covering those topics (seven of them received best paper awards). He has graduated seven doctoral students, currently supervises three doctoral students and three post-doc research associates. He is a principal investigator of EU-funded SAFIRE project, and a co-investigator in a number of other funded projects. He serves as the department's Internationalisation coordinator, and has held visiting faculty positions in five different countries. He is a member of the EPSRC College, a member of the HiPEAC European Network of Excellence, and a senior member of the IEEE.


Albrecht Mayer (Infineon):"Safety, security and availability – How will this fly for autonomous cars?"

Date: Friday, July 14th

Abstract: Cost effective, safe and secure systems with high availability are the key building blocks for more and more automated driving. One architectural challenge is to structure such systems in a way that the complexity and design effort is manageable on all levels. Multi-core microcontrollers currently play a key role due to their dependability, safety and hard real-time behavior. This talk will look at the challenges, tradeoffs and some of the solutions for such system architectures.

Bio: Albrecht Mayer is Senior Principal for Emulation Systems and Tooling at Infineon. In the past years he has been working on a multi-core microcontroller family architecture for a broad range of automotive applications, fulfilling highest requirements for safety, security, real-time behavior and availability under harsh conditions. He has many publications and holds more than 20 patents. Dr. Mayer received a Ph.D. degree in electrical engineering from the Technical University of Munich.