Open Hardware & RISC-V

Open-Source Software (OSS) has been around for quite some time, proving to be highly beneficial for both researchers/developers (as they can reuse code that is continuously monitored, changed and improved by the community) and companies (as some OSS alternatives are also free of charge, which effectively reduces their development and production costs). In the last few years, the same idea of openness has been extended to the hardware domain in what has been called Open-Source Hardware (OSH). Here, the challenges are multiple:

  • Need for open computing architectures
  • Need for open IP cores
  • Need for open toolchains and design environments

RISC-V, an open Instruction Set Architecture (ISA) developed by researchers at the University of California Berkeley in 2010, has become the de-facto solution to the first challenge. Apart from its open nature, this is also enforced by its highly modular implementation, which relies on a base ISA and one or more optional (i.e., up to the computer architect) extensions to address a wide range of processing profiles, from low-end microcontrollers to high-performance computing solutions like the accelerator in the European Processor Initiative (EPI), including domain-specific applications as well.
As an open architecture, RISC-V is highly appealing not only to the industry, but also to research entities that explore the whole processor ecosystem (from the design of the microarchitecture to the development of the software compiler stack). Currently, the Open Hardware paradigm is supported by several organizations: RISC-V International (a global non-profit association based in Switzerland with 2k+ members in more than 70 countries), which includes important actors from the computing market (e.g., Google, Intel) apart from academic institutions; CHIPS Alliance, which belongs to the Linux
Foundation and fosters open-source collaboration for hardware development; and the OpenHW Group, which promotes several microcontroller solutions built around RISC-V processors.