Andrés Otero was born in O Carballiño (Spain) in 1984. He received his M.Sc. degree in Telecommunication Engineering from the University of Vigo, where he graduated with honors in 2007. He received his Master of Research and Ph.D. degrees in Industrial Electronics from Universidad Politécnica de Madrid (UPM), in 2009 and 2014, respectively. From 2014 to 2015 he worked as a research engineer in the Galician Research and Development Center in Advanced Telecommunications (Gradiant), and from 2015 to 2016 he was an Engineer in Gsertel (Televés Group).
He is currently an Assistant Professor of electronics with the UPM, as well as a researcher in the Centro de Electrónica Industrial (CEI). His current research interests are focused on Embedded and Digital system design, Wireless Sensor Networks, Computer Vision, Evolvable Hardware and Reconfigurable Systems on FPGAs. During the last years, he has been involved in different research projects in these areas, and he is the author of more than 20 papers published in international conferences and journals. He has served as the Program Committee member of different international conferences in the field of reconfigurable systems, such as SPL, ERSA, ReConFig, DASIP and ReCoSoC.