Teresa Riesgo

 TITULACIÓN ACADÉMICA

 ACTIVIDAD EN EL MÁSTER

Enlaces a documentos relacionados

 
• A Binary Decision Diagram Structure for Probabilistic Switching Activity Estimation
  Autores: Felipe Machado, Yago Torroja, and Teresa Riesgo - 2008
  Journal Low Power Electronics 4, 247–262 (JOLPE)
 
• A Fast Emulation-Based NoC Prototyping Framework
  Autores: Yana E. Krasteva, Francisco Criado, Eduardo de la Torre and Teresa Riesgo - 2008
  International Conference on ReConFigurable Computing and FPGAs (ReConFig'08)
 
• A Piezoelectric minirheometer for measuring the viscosity of polymer microsamples
  Autores: A.M. Sánchez, R. Prieto, M. Laso, T. Riesgo - 2008
  IEEE Transactions on Industrial Electronics
 
• A BDD proposal for Probabilistic Switching Activity Estimation
  Autores: F. Machado, Y. Torroja, T. Riesgo - 2008
  International Conference on Design of Circuits and Integrated Systems (DCIS)
 
• FPGA implementation of an image recognition system based on tiny neural networks and on-line reconfiguration
  Autores: F. Moreno, J. Alarcón, R. Salvador, T. Riesgo - 2008
  Conference of the IEEE Industrial Electronics Society (IECON)
 
• NoC Emulation based on Partial Reconfiguration
  Autores: Y. E. Krasteva, F. Criado, E. de la Torre, T. Riesgo - 2008
  International Conference on Design of Circuits and Integrated Systems (DCIS)
 
• Wireless Sensor Networks Node with Remote HW/SW Reconfiguration Capabilities
  Autores: J. Portilla, Y. E. Krasteva, J.M. Carnicer, T. Riesgo - 2008
  International Conference on Design of Circuits and Integrated Systems (DCIS)
 
• Remote HW-SW Reconfigurable Wireless Sensor Nodes
  Autores: Yana E. Krasteva, J. Portilla, J. M. Carnicer, E. de la Torre and T. Riesgo - 2008
  Proceedings of IEEE Annual Conference of the IEEE Industrial Electronics Society (IECON'08)
 
• Virtual Architectures for Partial Runtime Reconfigurable Systems. Application to Network on Chip based SoC Emulation
  Autores: Yana E. Krasteva, E. de la Torre and T. Riesgo - 2008
  Proceedings of IEEE Annual Conference of the IEEE Industrial Electronics Society (IECON'08)
 
• Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level
  Autores: Felipe Machado, Teresa Riesgo, Yago Torroja - 2008
  Power And Timing Modeling, Optimization and Simulation (PATMOS)
 
• Architectural power analysis for intellectual property-based digital system
  Autores: Y.A. Durrani, T. Riesgo - 2007
  Journal of Low Power Electronics
 
• A Reconfigurable FPGA-Based Architecture for Modular Nodes in Wireless Sensor Networks
  Autores: J. Portilla, A. de Castro, T. Riesgo - 2007
  Southern conference on programmable logic (SPL)
 
• Towards fine and medium grain dynamic functional extraction for hw/sw acceleration
  Autores: V. Matev, E. de la Torre,T. Riesgo - 2007
  Southern conference on programmable logic (SPL)
 
• Architectural power estimation technique for IP-based System-on-Chip
  Autores: Y.A. Durrani, A. Abril, T. Riesgo - 2007
  IEEE International Symposium on Industrial Electronics (ISIE)
 
• Efficient power macromodeling technique for IP-based digital systems
  Autores: Y.A. Durrani, A. Abril, T. Riesgo - 2007
  IEEE International Symposium on Circuits and Systems (ISCAS)
 
• High level power estimation for digital system
  Autores: Yaseer A. Durrani, Ana Abril, T. Riesgo - 2007
  SPIE Synposiym on Microtechnologies for the New Millenium
 
• Integrated hardware interfaces for modular sensor networks
  Autores: J. Portilla, A. Abril, A. de Castro, T. Riesgo - 2007
  SPIE European Symposium on Microtechnologies for the New Millennium
 
• Reconfigurable Heterogeneous Communications and Core Reallocation for Dynamic HW Task Management
  Autores: Yana E. Krasteva, Eduardo de la Torre, Teresa Riesgo - 2007
  IEEE International Symposium on Circuits and Systems (ISCAS)
 
• Creating partially reconfigurable systems
  Autores: Y. Esteves, E. de la Torre, T. Riesgo - 2007
  International Conference on Design of Circuits and Integrated Systems (DCIS)
 
• Space Design Exploration of a Viterbi-based ECC Encoding/Decoding Scheme by Wireless Transmission Emulation
  Autores: E. Peña, A. González, E. de la Torre, T. Riesgo - 2007
  International Conference on Design of Circuits and Integrated Systems (DCIS)
 
• Using wireless sensor networks for an interactive musical application
  Autores: J. Portilla, E. Esteban, J. Alcázar, A. Abril, Y. Torroja, T. Riesgo - 2007
  International Conference on Design of Circuits and Integrated Systems (DCIS)
 
• A digital system to emulate wireless networks
  Autores: E. Peña, E. de la Torre, A. de Castro, T. Riesgo - 2007
  IET Comput.. Tech.
 
• Rapid prototyping for multi-application sensor networking
  Autores: J. Portilla, A. de Castro, A. Abrio, T. Riesgo - 2007
  SPIE Newsroom
 
• Modular Architecture for Wireless Sensor Network Nodes
  Autores: J. Portilla, A. de Castro, E. de la Torre, T. Riesgo - 2006
  Fifth Internacional Conference on Information Processing in Sensor Networks (IPSN)
 
• Power estimation for register transfer level by genetic algorithm
  Autores: Yaseer A. Durrani, T. Riesgo, F. Machado - 2006
  Proceedings for International Conference on Informatics in Control Automation and Robotics
 
• A Hardware Library for Sensors/Actuators in Sensor Networks
  Autores: J. Portilla, J. L. Buron, A. de Castro, T. Riesgo - 2006
  IEEE International Conference on Electronics, Circuits and Systems (ICECS)
 
• Power macromodeling for IP modules
  Autores: Y. A. Durrani, T. Riesgo - 2006
  IEEE International Conference on Electronics, Circuits and Systems (ICECS)
 
• Partial Reconfiguration for Core Reallocation and Flexible Communications
  Autores: Y. E. Krasteva, E. de la Torre, Teresa Riesgo - 2006
  International Workshop on Reconfigurable Communication-Centric System-on-Chips
 
• Power macromodeling for high level power estimation
  Autores: Y.A. Durrani, T. Riesgo - 2006
  Workshop on Reconfigurable Communication-Centric System on Chips
 
• Statistical power estimation for register transfer level
  Autores: Yaseer A. Durrani, T. Riesgo, F. Machado - 2006
  nternational Conference on Mixed Design of Integrated Circuits and Systems
 
• A modular architecture for nodes in wireless sensor networks
  Autores: J. Portilla, A. de Castro, E. de la Torre, T. Riesgo - 2006
  Journal of Universal Computer Science
 
• Ubiquitous computing and ambient intelligence: new challenges for computing
  Autores: J. Bravo, X. Alamán, T. Riesgo - 2006
  Journal of Universal Computer Science
 
• A VHDL Library for Sensors/Actuators in Sensor Networks
  Autores: J. Portilla, J.L. Buron, A. de Castro, T. Riesgo - 2006
  Proceedings of International Conference on Design of Circuits and Integrated Systems (DCIS)
 
• An Activity Estimation Tool for VHDL-RTL Combinational Circuits
  Autores: F. Machado, A. Abril, Y. Torroja, T. Riesgo - 2006
  Proceedings of International Conference on Design of Circuits and Integrated Systems (DCIS)
 
• Applying Partial Reconfiguration for Debugging and Monitoring FPGA based Reconfigurable Systems
  Autores: Y. Krasteva, E. de la Torre, T. Riesgo - 2006
  Proceedings of International Conference on Design of Circuits and Integrated Systems (DCIS)
 
• Power macromodelling technique for IP-based systems
  Autores: Y.A. Durrani, T. Riesgo, A. Abril - 2006
  Proceedings of International Conference on Design of Circuits and Integrated Systems (DCIS)
 
• Power estimation for IP-based modules
  Autores: Yaseer A. Durrani, T. Riesgo - 2006
  International Symposium on System-on-Chip
 
• Statistical power estimation for IP-based design
  Autores: Y. A. Durrani, T. Riesgo - 2006
  IEEE Industrial Electronics Conference (IECON)
 
• High level statistical power estimation
  Autores: Y.A. Durrani, T. Riesgo - 2006
  International Workshop on Symbolyc Method and Applications to Circuit Design
 
• A Method for Switching Activity Analysis of VHDL-RTL Combinatorial Circuits
  Autores: Felipe Machado, Teresa Riesgo, Yago Torroja - 2006
  International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS)
 
• A Method for Switching Activity Analysis of VHDL-RTL Combinatorial Circuits
  Autores: Felipe Machado, Teresa Riesgo, Yago Torroja - 2006
  Lecture Notes in Computer Science
 
• Microelectrónica. Circuitos y Sistemas. Una perspectiva práctica.
  Autores: F. Moreno, T. Riesgo - 2006
  www.lulu.com (ID: 536883)
 
• Switching Activity Propagation of VHDL-RTL Combinational Designs through an Automated Tool.
  Autores: F. Machado, T. Riesgo, Y. Torroja - 2005
  IEEE International Conference on Electronics, Circuits and Systems
  Presentación: Switching Activity Propagation of VHDL-RTL Combinational Designs through an Automated Tool.
 
• Exploiting VHDL-RTL fetarues to reduce the complexity of power estimation in combinational circuits
  Autores: "F. Machado; Y. Torroja; T. Riesgo" - 2005
  PRIME-EPFL
  Presentación: Exploiting VHDL-RTL fetarues to reduce the complexity of power estimation in combinational circuits
 
• Flexible Core reallocation for Virtex II structures
  Autores: "Y. Krasteva; A.B. Jimeno; E. de la Torre; T. Riesgo" - 2005
  International Conference on Engineering of Reconfigurable Sustems and Algorithms (ERSA)
 
• Straight method for reallocation of complex cores by dynamic reconfiguration in virtex II FPGAs
  Autores: Y.E. Krasteva, A.B. Jimeno, E. de la Torre, T. Riesgo - 2005
  Internationatal Workshop on Rapid System Prototyping (RSP)
 
• A functional validation methodology based on error models for measuring the quality of digital integratted circuits
  Autores: "C. López; L. Entrena; T. Riesgo; J. Uceda" - 2005
  SPIE: VLSI Circuits and Systems II
 
• Integrated cifcuit debur through FPGA emulation. Application to a PIC-18 macrocell
  Autores: "M. García; E. de la Torre; F. Casado; L. Entrena; T. Riesgo" - 2005
  SPIE: VLSI Circuits and Systems II
 
• A Digital System to emulate Wireless Networks
  Autores: E. Peña, E. de la Torre, A. de Castro, T. Riesgo - 2005
  Design of Circuit and Integrated Systems (DCIS)
 
• Modular Architecture for Smart Sensor Network Nodes
  Autores: J. Portilla, A. de Castro, E. de la Torre, T. Riesgo - 2005
  Design of Circuit and Integrated Systems (DCIS)
 
• Teaching embedded systems and microcontrollers using scale models
  Autores: "Torroja, Y.; Garcia, O.; Riesgo, T.; de la Torre, E.;" - 2005
  IEEE Industrial Electronics Conference (IECON)
 
• ENAMORADO: Enabling Nomadic Agents in a Multimedia ORiented Architecture of Distributed Objects
  Autores: "Y. Krasteva; C. Papagianni ; E. Kosmatos; E. de la Torre; I.S. Venieris; T. Riesgo" - 2005
  Innovation and the Knowledge Economy
 
• An Approach to Smart Sensor Network Nodes for Distributed Measurement and Control
  Autores: "J. Portilla: A. de Castro; T. Riesgo" - 2005
  Ubiquitiuous Computing and Ambient Intelligence (UCAml)
 
• ENAMORADO:Una experiencia hacia los terminales móviles reconfigurables en entornos multimedia
  Autores: "X. Peña; Y. Krasteva; A.B. Jimeno; E. de la Torre;T. Riesgo" - 2005
  Ubiquitiuous Computing and Ambient Intelligence (UCAml)
 
• Hardware and software debugging of FPGA based microprocessor systems through debug logic insertion
  Autores: "M. García; E. de la Torre; Ariza, E.; T. Riesgo" - 2004
  Field Programmable Logic
 
• A methodology to design custom hardware digital controllers for switching power converters
  Autores: "A. de Castro; T. Riesgo; O. García; J. Uceda" - 2004
  IEEE Power Electronics Specialists Conference (PESC)
  Presentación: A methodology to design custom hardware digital controllers for switching power converters
 
• Digital phase-shifting for multiphase converters
  Autores: "A. de Castro; Zumel, P.; O. García; T. Riesgo" - 2004
  Design of Circuit and Integrated Systems (DCIS)
 
• Concurrent and simple digital controller of an AC/DC converter with power factor correction based on an FPGA
  Autores: "A. de Castro; P. Zumel; O. García; T. Riesgo; J. Uceda" - 2003
  IEEE Transactions on Power Electronics
 
• Design Guidelines for DC/DC converters with Dynamic Voltage Scaling
  Autores: "A. Soto; P. Alou; J.A. Oliver; J.A. Cobos; T. Riesgo" - 2003
  EPE Journal
 
• Digital control in multi-phase DC-DC converters
  Autores: "A. de Castro; P. Zumel; O. García; T. Riesgo" - 2003
  EPE Journal
 
• Comparing VHDL and VHDL-AMS for Modelling and Simulation of Power Converters with Digital Control
  Autores: "A. de Castro; T. Riesgo; O. García; R. Prieto" - 2003
  Design of Circuits and Integrated Systems Conference (DCIS)
 
• ENAMORADO: Reconfiguración Parcial de FPGAs en dispositivos móviles
  Autores: A. Jimeno, Y. Krasteva, E. de la Torre, T. Riesgo - 2003
  Jornadas sobre Computación Reconfigurable y Aplicaciones (JCRA)
 
• SmS: Un sistema en chip para micro-transductores inteligentes compatible con el estándar IEEE-1451
  Autores: "A. de Castro; T. Riesgo" - 2003
  Revista Siglo XXI
 
• A system-on chip for Smart sensors
  Autores: "A. de Castro; J.M. Chaquet; E. Morejón; T. Riesgo; J. Uceda" - 2002
  IEEE International Symposium on Industrial Electronics (ISIE)
 
• Non-Intrusive Debugging using the JTAG interface of FPGA-Based Prototypes
  Autores: "E. de la Torre; M. García; T. Riesgo; Y. Torroja; J. Uceda" - 2002
  IEEE International Symposium on Industrial Electronics (ISIE)
 
• Concurrent and simple digital controller of an AC/DC converter with power factor correction
  Autores: "P. Zumel; A. de Castro; O. García; T. Riesgo; J. Uceda" - 2002
  IEEE Applied Power Electronics Conference (APEC)
 
• Hardware Reconfigurable
  Autores: "E. de la Torre; Y. Torroja; T. Riesgo; J. Uceda" - 2002
  INDUMÁTICA
 
• A Modular Environment for Learning Digital Control Applications
  Autores: "Y. Torroja; R. Velasco; E. Angulo; T. Riesgo; E. de la Torre" - 2002
  European Workshop on Microelectronics Education (EWME)
 
• Custom Hardware IEEE 1451.2 Implementation for Smart Transducers
  Autores: "A. de Castro; T. Riesgo; E. de la Torre; Y. Torroja; J. Uceda" - 2002
  IEEE Industrial Electronics Conference (IECON)
 
• FPGS Debugging through JTAG: Developing highly configurable debug modules
  Autores: "M. García; E. de la Torre; T. Riesgo; L. Entrena" - 2002
  Design of Circuits and Integrated Systems Conference (DCIS)
 
• Reusable and reconfigurable system for sensor interfacing and control
  Autores: "A. de Castro; T. Riesgo; J. Uceda" - 2002
  Design of Circuits and Integrated Systems Conference (DCIS)
 
• Diseño de sistemas electrónicos basados en la reconfiguración del hardware
  Autores: T. Riesgo, E. de la Torre, Y. Torroja, J. Uceda - 2001
  INDUMÁTICA
 
• Highly configurable solutions for Microprocessor-Bassed Control Boards
  Autores: "T. Riesgo; E. de la Torre; M. García; A. de Castro; Y. Torroja; J. Uceda" - 2001
  Design, Automation and Test in Europe (DATE)
 
• Debugging and Tracing in JTAG-Compatible FPGA-Based Designs
  Autores: "M. Garcia; A. de Castro; E. de la Torre; T. Riesgo; J. Uceda" - 2001
  Design of Circuits and Integrated Systems Conference (DCIS)
 
• FPGA-based Control of a Flyback Converter with Power Factor Correction
  Autores: "A. de Castro; P. Zumel; O. García; T. Riesgo; J. Uceda" - 2001
  Design of Circuits and Integrated Systems Conference (DCIS)
 
• Mantenimiento de configuraciones y depuración de hardware mediante la herramienta CHDT
  Autores: E. de la Torre, M. García, A. de Castro, T. Riesgo, J. Uceda - 2001
  Jornadas sobre Computación Reconfigurable y Aplicaciones (JCRA)
 
• A simple digital hardware to control a PFC converter
  Autores: "P. Zumel; A. de Castro; O. García; T. Riesgo; J. Uceda" - 2001
  IEEE Industrial Electronics Control and Instrumentation (IECON)
 
• Application of VHDL Features for Optimisation of Functional Validation Quality Measurement
  Autores: "C. López; T. Riesgo; Y. Torroja; J. Uceda; L. Entrena" - 2001
  System-on-Chip Methodologies & Design Languages Edited by P.J. Ashenden, J.P. Mermet and R. Seepold, Kluwer Academic Publishers,
 
• ARDID: A tool and a model for the quality analysis of VHDL based designs
  Autores: "Y. Torroja; F. Machado; E. de la Torre; T. Riesgo; J. Uceda" - 2001
  Kluwer Academic Publishers
 
• Reusable, reconfigurable and reliable HW for rapid prototyping of control boards Design of Hardware/Software. Embedded Systems
  Autores: "E. de la Torre; Y. Torroja; T. Riesgo; J. Uceda" - 2001
  Eugenio Villar (ed.) Servicio de Publicaciones de la Universidad de Cantabria
 
• Two experiences in virtual prototyping usign VHDL and C Design of Hardware/Software. Embedded Systems
  Autores: "E. de la Torre; Y. Torroja; T. Riesgo; J. Uceda" - 2001
  Eugenio Villar (ed.) Servicio de Publicaciones de la Universidad de Cantabria